The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Jan. 23, 2012
Dae-hyuk Kang, Hwaseong-si, KR;
Bo-un Yoon, Seoul, KR;
Kun-tack Lee, Suwon-si, KR;
Woo-gwan Shim, Yongin-si, KR;
Ji-hoon Cha, Seoul, KR;
Im-soo Park, Seongnam-si, KR;
Hyo-san Lee, Suwon-si, KR;
Young-hoo Kim, Hwaseong-si, KR;
Jung-min OH, Incheon, KR;
Dae-Hyuk Kang, Hwaseong-si, KR;
Bo-Un Yoon, Seoul, KR;
Kun-Tack Lee, Suwon-si, KR;
Woo-Gwan Shim, Yongin-si, KR;
Ji-Hoon Cha, Seoul, KR;
Im-Soo Park, Seongnam-si, KR;
Hyo-San Lee, Suwon-si, KR;
Young-Hoo Kim, Hwaseong-si, KR;
Jung-Min Oh, Incheon, KR;
Abstract
In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.