The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2014

Filed:

Jun. 24, 2011
Applicants:

Yong-lack Choi, Seoul, KR;

Chang-hyun Cho, Yongin-si, KR;

Seung-pil Chung, Seoul, KR;

Hyun-seok Jang, Seoul, KR;

Du-heon Song, Seongnam-si, KR;

Jung-dal Choi, Seongnam-si, KR;

Inventors:

Yong-lack Choi, Seoul, KR;

Chang-hyun Cho, Yongin-si, KR;

Seung-pil Chung, Seoul, KR;

Hyun-seok Jang, Seoul, KR;

Du-heon Song, Seongnam-si, KR;

Jung-dal Choi, Seongnam-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.


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