The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2014

Filed:

Sep. 22, 2011
Applicants:

Yasushi Inagaki, Ibi-gun, JP;

Motoo Asai, Ibi-gun, JP;

Dongdong Wang, Ibi-gun, JP;

Hideo Yabashi, Ibi-gun, JP;

Seiji Shirai, Ibi-gun, JP;

Inventors:

Yasushi Inagaki, Ibi-gun, JP;

Motoo Asai, Ibi-gun, JP;

Dongdong Wang, Ibi-gun, JP;

Hideo Yabashi, Ibi-gun, JP;

Seiji Shirai, Ibi-gun, JP;

Assignee:

Ibiden Co., Ltd., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a printed circuit board including providing a first resin substrate having a resin plate and a circuit pattern formed on a surface of the resin plate, providing a second resin substrate having a resin plate and an accommodation portion formed in the resin plate of the second substrate, connecting an electrode of a capacitor to the circuit pattern of the first substrate with a bonding material such that the capacitor is mounted to the first substrate, attaching the second substrate to the resin substrate through a bonding resin layer such that the capacitor on the first substrate is accommodated in the accommodation portion of the second substrate, and forming a via hole in the first substrate such that the via hole is electrically connected to the electrode of the capacitor in the accommodation portion of the second substrate.


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