The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2014
Filed:
Jul. 26, 2012
Margaret R. Charlebois, Jericho, VT (US);
Rashmi D. Chatty, Williston, VT (US);
Christopher D. Hanudel, Essex Junction, VT (US);
Robert D. Herzl, South Burlington, VT (US);
David W. Milton, Underhill, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Paul M. Schanely, Essex Junction, VT (US);
Matthew P. Szafir, Williston, VT (US);
Tad J. Wilder, South Hero, VT (US);
Margaret R. Charlebois, Jericho, VT (US);
Rashmi D. Chatty, Williston, VT (US);
Christopher D. Hanudel, Essex Junction, VT (US);
Robert D. Herzl, South Burlington, VT (US);
David W. Milton, Underhill, VT (US);
Clarence R. Ogilvie, Huntington, VT (US);
Paul M. Schanely, Essex Junction, VT (US);
Matthew P. Szafir, Williston, VT (US);
Tad J. Wilder, South Hero, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.