The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8749260 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 10, 2014

Filed:

Nov. 16, 2010
Applicants:

Yasuo Tokunaga, Gunma, JP;

Yoshio Komoto, Gunma, JP;

Inventors:

Yasuo Tokunaga, Gunma, JP;

Yoshio Komoto, Gunma, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test.


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Tokunaga, Yasuo. (2014). Test wafer unit and test system (U.S. Patent No. 8749260). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8749260

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