The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2014
Filed:
Dec. 22, 2009
Xianyu Wenxu, Yongin-si, KR;
Jung-hyun Lee, Suwon-si, KR;
Dong-joon MA, Anyang-si, KR;
Yeon-hee Kim, Seoul, KR;
Yong-young Park, Daejeon, KR;
Chang-soo Lee, Suwon-si, KR;
Xianyu Wenxu, Yongin-si, KR;
Jung-hyun Lee, Suwon-si, KR;
Dong-joon Ma, Anyang-si, KR;
Yeon-hee Kim, Seoul, KR;
Yong-young Park, Daejeon, KR;
Chang-soo Lee, Suwon-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a substrate and a plurality of semiconductor pillars on the substrate. A plurality of control gate electrodes may be stacked on the substrate and intersecting the plurality of semiconductor pillars. A plurality of dummy electrodes may be stacked adjacent to the plurality of control gate electrodes on the substrate, the plurality of dummy electrodes being spaced apart from the plurality of control gate electrodes. A plurality of via plugs may be connected to the plurality of control gate electrodes. A plurality of wordlines may be on the plurality of via plugs. Each of the plurality of via plugs may penetrate a corresponding one of the plurality of control gate electrodes and at least one of the plurality of dummy electrodes.