The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2014
Filed:
Jul. 19, 2012
Charles L. Arvin, Poughkeepsie, NY (US);
Eric D. Perfecto, Poughkeepsie, NY (US);
Wolfgang Sauter, Hinesburg, VT (US);
Jennifer D. Schuler, Wappingers Falls, NY (US);
Charles L. Arvin, Poughkeepsie, NY (US);
Eric D. Perfecto, Poughkeepsie, NY (US);
Wolfgang Sauter, Hinesburg, VT (US);
Jennifer D. Schuler, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side.