The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
Feb. 16, 2012
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Subramanian S. Iyer, Mount Kisco, NY (US);
Steven J. Koester, Ossining, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Roy R. Yu, Poughkeepsie, NY (US);
Mukta G. Farooq, Hopewell Junction, NY (US);
Robert Hannon, Wappingers Falls, NY (US);
Subramanian S. Iyer, Mount Kisco, NY (US);
Steven J. Koester, Ossining, NY (US);
Sampath Purushothaman, Yorktown Heights, NY (US);
Roy R. Yu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.