The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2014

Filed:

Jun. 07, 2012
Applicants:

Frank Johnson, Wappingers Falls, NY (US);

Olivier Menut, Saint-Martin-d'Hères, FR;

Marc Tarabbia, Pleasant Valley, NY (US);

Gregory A. Northrop, Putnam Valley, NY (US);

Inventors:

Frank Johnson, Wappingers Falls, NY (US);

Olivier Menut, Saint-Martin-d'Hères, FR;

Marc Tarabbia, Pleasant Valley, NY (US);

Gregory A. Northrop, Putnam Valley, NY (US);

Assignees:

GLOBALFOUNDRIES, Inc., Grand Cayman, KY;

International Business Machines, Armonk, NY (US);

STMicroelectronics, Inc., Coppell, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.


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