The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
May. 24, 2012
Amol Joshi, Sunnyvale, CA (US);
John Foster, Mountain View, CA (US);
Zhendong Hong, San Jose, CA (US);
Olov Karlsson, San Jose, CA (US);
Bei LI, Fremont, CA (US);
Usha Raghuram, Saratoga, CA (US);
Amol Joshi, Sunnyvale, CA (US);
John Foster, Mountain View, CA (US);
Zhendong Hong, San Jose, CA (US);
Olov Karlsson, San Jose, CA (US);
Bei Li, Fremont, CA (US);
Usha Raghuram, Saratoga, CA (US);
Intermolecular, Inc., San Jose, CA (US);
Abstract
Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.