The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2014
Filed:
Dec. 17, 2010
Jan Van Kempen, Cuyk, NL;
René Wilhelmus Johannes Maria Van Den Boomen, Asten, NL;
Emiel DE Bruin, Elst, NL;
Jan van Kempen, Cuyk, NL;
René Wilhelmus Johannes Maria van den Boomen, Asten, NL;
Emiel de Bruin, Elst, NL;
NXP B.V., Eindhoven, NL;
Abstract
The invention relates to a method of manufacturing a semiconductor device, the method comprising: i) providing a substrate carrier comprising a substrate layer and a patterned conductive layer, wherein the patterned conductive layer defines contact pads; ii) partially etching the substrate carrier using the patterned conductive layer as a mask defining contact regions in the substrate layer; iii) providing the semiconductor chip; iv) mounting said semiconductor chip with the adhesive layer on the patterned conductive layer such that the semiconductor chip covers at least one of the trenches and part of the contact pads neighboring the respective trench are left uncovered for future wire bonding; v) providing wire bonds between respective terminals of the semiconductor chip and respective contact pads of the substrate carrier; vi) providing a molding compound covering the substrate carrier and the semiconductor chip, and vii) etching the backside (S) of the substrate carrier to expose the molding compound in the trenches. The invention further relates to a semiconductor device manufactured with such method, and to a printed-circuit board comprising such semiconductor device. The invention enables a reduced minimum bondpad pitch. An embodiment of the invention has a by-design-wettable terminal side at the perimeter of the device. This latest mentioned feature enables automated board inspection w.r.t. board mounting quality.