The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2014
Filed:
Mar. 09, 2012
Yi-tang Lin, Hsinchu, TW;
Cheok-kei Lei, Andar AC, MO;
Shu-yu Chen, Hsinchu, TW;
Yu-ning Chang, Hsinchu, TW;
Hsiao-hui Chen, Hsinchu, TW;
Chih-sheng Chang, Hsinchu, TW;
Chien-wen Chen, Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Yi-Tang Lin, Hsinchu, TW;
Cheok-Kei Lei, Andar AC, MO;
Shu-Yu Chen, Hsinchu, TW;
Yu-Ning Chang, Hsinchu, TW;
Hsiao-Hui Chen, Hsinchu, TW;
Chih-Sheng Chang, Hsinchu, TW;
Chien-Wen Chen, Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Abstract
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.