The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2014

Filed:

Apr. 27, 2012
Applicants:

Oleg Golonzka, Beaverton, OR (US);

Hemant Deshpande, Beaverton, OR (US);

Ajay K Sharma, Beaverton, OR (US);

Cory Weber, Hillsboro, OR (US);

Ashutosh Ashutosh, Hillsboro, OR (US);

Inventors:

Oleg Golonzka, Beaverton, OR (US);

Hemant Deshpande, Beaverton, OR (US);

Ajay K Sharma, Beaverton, OR (US);

Cory Weber, Hillsboro, OR (US);

Ashutosh Ashutosh, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.


Find Patent Forward Citations

Loading…