The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2014
Filed:
Jul. 20, 2012
Timothy H. Daubenspeck, Colchester, VT (US);
Brian M. Erwin, Lagrangeville, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
Wolfgang Sauter, Hinesburg, VT (US);
George J. Scott, Chandler, AZ (US);
Timothy H. Daubenspeck, Colchester, VT (US);
Brian M. Erwin, Lagrangeville, NY (US);
Jeffrey P. Gambino, Westford, VT (US);
Wolfgang Sauter, Hinesburg, VT (US);
George J. Scott, Chandler, AZ (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.