The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2014
Filed:
Oct. 02, 2012
Semiconductor Technology Academic Research Center, Kanagawa, JP;
National University Corporation Tohoku University, Miyagi, JP;
Junichi Koike, Sendai, JP;
Yoshito Fujii, Sendai, JP;
Jun Iijima, Sendai, JP;
Noriyoshi Shimizu, Kawasaki, JP;
Kazuyoshi Maekawa, Itami, JP;
Koji Arita, Kanagawa, JP;
Ryotaro Yagi, Hamamatsu, JP;
Masaki Yoshimaru, Hachioji, JP;
Semiconductor Technology Academic Research Center, Kanagawa, JP;
National University Corporation Tohoku University, Miyagi, JP;
Abstract
A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.