The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2014

Filed:

Feb. 16, 2010
Applicants:

Sanjeev Jahagirdar, Folsom, CA (US);

Varghese George, Folsom, CA (US);

John B. Conrad, Kwajalein, MH;

Robert Milstrey, Citrus Heights, CA (US);

Stephen A. Fischer, Gold River, CA (US);

Alon Naveh, Ramat Hasharon, IL;

Shai Rotem, Haifa, IL;

Inventors:

Sanjeev Jahagirdar, Folsom, CA (US);

Varghese George, Folsom, CA (US);

John B. Conrad, Kwajalein, MH;

Robert Milstrey, Citrus Heights, CA (US);

Stephen A. Fischer, Gold River, CA (US);

Alon Naveh, Ramat Hasharon, IL;

Shai Rotem, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 12/00 (2006.01); G06F 15/00 (2006.01); G06F 11/00 (2006.01); G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
Abstract

For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.


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