The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2014
Filed:
Jul. 13, 2009
Seung Wook Park, Suwon-si, KR;
Young DO Kweon, Seoul, KR;
Jin Gu Kim, Suwon-si, KR;
Ju Pyo Hong, Suwon-si, KR;
Hee Kon Lee, Hwaseong-si, KR;
Hyung Jin Jeon, Gunpo-si, KR;
Jing LI Yuan, Suwon-si, KR;
Jong Yun Lee, Incheon-si, KR;
Seung Wook Park, Suwon-si, KR;
Young Do Kweon, Seoul, KR;
Jin Gu Kim, Suwon-si, KR;
Ju Pyo Hong, Suwon-si, KR;
Hee Kon Lee, Hwaseong-si, KR;
Hyung Jin Jeon, Gunpo-si, KR;
Jing Li Yuan, Suwon-si, KR;
Jong Yun Lee, Incheon-si, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.