The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 2014

Filed:

Apr. 26, 2012
Applicants:

Po-nien Chen, Miaoli, TW;

Jin-aun NG, Hsinchu, TW;

Ming Zhu, Singapore, SG;

Bao-ru Young, Zhubei, TW;

Hak-lay Chuang, Singapore, SG;

Inventors:

Po-Nien Chen, Miaoli, TW;

Jin-Aun Ng, Hsinchu, TW;

Ming Zhu, Singapore, SG;

Bao-Ru Young, Zhubei, TW;

Hak-Lay Chuang, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.


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