The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2014
Filed:
Dec. 10, 2009
Alan B. Botula, Essex Junction, VT (US);
John J. Ellis-monaghan, Grand Isle, VT (US);
Alvin J. Joseph, Williston, VT (US);
Max G. Levy, Essex Junction, VT (US);
Richard A. Phelps, Colchester, VT (US);
James A. Slinkman, Montpelier, VT (US);
Randy L. Wolf, Essex Junction, VT (US);
Alan B. Botula, Essex Junction, VT (US);
John J. Ellis-Monaghan, Grand Isle, VT (US);
Alvin J. Joseph, Williston, VT (US);
Max G. Levy, Essex Junction, VT (US);
Richard A. Phelps, Colchester, VT (US);
James A. Slinkman, Montpelier, VT (US);
Randy L. Wolf, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.