The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Apr. 15, 2008
Takeshi Segawa, Tokyo, JP;
Naofumi Izumi, Tokyo, JP;
Takeshi Segawa, Tokyo, JP;
Naofumi Izumi, Tokyo, JP;
Lintec Corporation, Tokyo, JP;
Abstract
A method for producing a chip () in which a die bonding adhesive layer () and a wafer () are laminated on a close-contact layer () of a fixing jig (), the chip is formed by completely cutting the wafer and the die bonding adhesive layer and then the chip is picked up together with the die bonding adhesive layer from the fixing jig by deforming the close-contact layer of the fixing jig. In the method the fixing jig is provided with the close-contact layer and a jig base () that is provided with a plurality of protrusions () on one side and a sidewall () at the outer circumference section of the one side. The close-contact layer is laminated on the surface of the jig base provided with the protrusions and is bonded on the upper surface of the sidewall. On the surface of the jig base provided with the protrusions, a partitioned space is formed by the close-contact layer, the protrusions, and the sidewall. The jig base is provided with at least one through hole () penetrating the outside and the partitioned space, and the close-contact layer can be deformed by sucking air from the partitioned space via the through hole of the fixing jig.