The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2014
Filed:
Aug. 25, 2011
Sheng-huei Dai, Taitung County, TW;
Rai-min Huang, Taipei, TW;
Chen-hua Tsai, Hsinchu County, TW;
Shih-hung Tsai, Tainan, TW;
Chien-ting Lin, Hsinchu, TW;
Sheng-Huei Dai, Taitung County, TW;
Rai-Min Huang, Taipei, TW;
Chen-Hua Tsai, Hsinchu County, TW;
Shih-Hung Tsai, Tainan, TW;
Chien-Ting Lin, Hsinchu, TW;
United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.