The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2014

Filed:

Oct. 05, 2007
Applicants:

Ruigang LI, Austin, TX (US);

Jingrong Zhou, Austin, TX (US);

David Donggang Wu, Austin, TX (US);

Zhonghai Shi, Austin, TX (US);

James F. Buller, Austin, TX (US);

Akif Sultan, Austin, TX (US);

Fred Hause, Austin, TX (US);

Donna Michael, Cedar Park, TX (US);

Inventors:

Ruigang Li, Austin, TX (US);

Jingrong Zhou, Austin, TX (US);

David Donggang Wu, Austin, TX (US);

Zhonghai Shi, Austin, TX (US);

James F. Buller, Austin, TX (US);

Mark W. Michael, Cedar Park, TX (US);

Akif Sultan, Austin, TX (US);

Fred Hause, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/02 (2006.01); G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.


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