The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2014
Filed:
Oct. 28, 2011
Albert Bergemont, Palo Alto, CA (US);
Uppili Sridhar, Cupertino, CA (US);
Joseph Ellul, San Jose, CA (US);
Yi-sheng Anthony Sun, San Jose, CA (US);
Elliott Simons, Southborough, MA (US);
Albert Bergemont, Palo Alto, CA (US);
Uppili Sridhar, Cupertino, CA (US);
Joseph Ellul, San Jose, CA (US);
Yi-Sheng Anthony Sun, San Jose, CA (US);
Elliott Simons, Southborough, MA (US);
Maxim Integrated Products, Inc., Sunnyvale, CA (US);
Abstract
A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.