The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8674507 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 18, 2014

Filed:

May. 27, 2004
Applicants:

Chien-kang Chou, Shin Hwa Town, TW;

Chiu-ming Chou, Kao-Hsiung, TW;

Li-ren Lin, Bali Township, Taipei Country, TW;

Chu-fu Lin, Kaohsiung, TW;

Inventors:

Chien-Kang Chou, Shin Hwa Town, TW;

Chiu-Ming Chou, Kao-Hsiung, TW;

Li-Ren Lin, Bali Township, Taipei Country, TW;

Chu-Fu Lin, Kaohsiung, TW;

Assignee:

Megit Acquisition Corp., San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.


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Chou, Chien-Kang. (2014). Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer (U.S. Patent No. 8674507). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8674507

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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