The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2014

Filed:

Oct. 05, 2010
Applicants:

Krishna Kumar Bhuwalka, Hsin-Chu, TW;

Ching-ya Wang, Taipei, TW;

Ken-ichi Goto, Hsin-Chu, TW;

Wen-chin Lee, Hsin-Chu, TW;

Carlos H. Diaz, Mountain View, CA (US);

Inventors:

Krishna Kumar Bhuwalka, Hsin-Chu, TW;

Ching-Ya Wang, Taipei, TW;

Ken-Ichi Goto, Hsin-Chu, TW;

Wen-Chin Lee, Hsin-Chu, TW;

Carlos H. Diaz, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.


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