The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2014
Filed:
Mar. 01, 2011
Woo-song Ahn, Hwaseong-si, KR;
Satoru Yamada, Seoul, KR;
Young-jin Choi, Hwaseong-si, KR;
Seung-uk Han, Suwon-si, KR;
Kyo-suk Chae, Suwon-si, KR;
Woo-Song Ahn, Hwaseong-si, KR;
Satoru Yamada, Seoul, KR;
Young-Jin Choi, Hwaseong-si, KR;
Seung-Uk Han, Suwon-si, KR;
Kyo-Suk Chae, Suwon-si, KR;
Samsung Electronics Co., Ltd., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.