The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2014

Filed:

Jun. 22, 2010
Applicants:

Hsin-hui Lee, Kaohsiung, TW;

William Cheng, Hsinchu, TW;

Inventors:

Hsin-Hui Lee, Kaohsiung, TW;

William Cheng, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 21/46 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer is provided having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies are provided, each of the dies is bonded to one of the plurality of semiconductor chips. One or more trenches are formed on the chip side of the wafer. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material, the protecting material substantially filling the one or more trenches. The wafer is diced to separate it into individual semiconductor packages.


Find Patent Forward Citations

Lee, Hsin-Hui. (2014). Structure and method of wafer level chip molded packaging (U.S. Patent No. 8647963). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8647963

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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