The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2014

Filed:

Jan. 12, 2007
Applicants:

Krishnamurthy Bhaskar, San Jose, CA (US);

Mark J. Roulo, Mountain View, CA (US);

John S. Taylor, San Jose, CA (US);

Lawrence R. Miller, Los Altos, CA (US);

Paul T. Russell, Scotts Valley, CA (US);

Jason Z. Lin, Saratoga, CA (US);

Eliezer Rosengaus, Palo Alto, CA (US);

Richard M. Wallingford, San Jose, CA (US);

Kishore Bubna, Fremont, CA (US);

Inventors:

Krishnamurthy Bhaskar, San Jose, CA (US);

Mark J. Roulo, Mountain View, CA (US);

John S. Taylor, San Jose, CA (US);

Lawrence R. Miller, Los Altos, CA (US);

Paul T. Russell, Scotts Valley, CA (US);

Jason Z. Lin, Saratoga, CA (US);

Eliezer Rosengaus, Palo Alto, CA (US);

Richard M. Wallingford, San Jose, CA (US);

Kishore Bubna, Fremont, CA (US);

Assignee:

KLA-Tencor Corporation, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

An inspection system for detecting anomalies on a substrate. The inspection system has a sensor array for generating image data. A first high speed network is coupled to the sensor array and receives and communicates the image data. An array of process nodes is coupled to the first high speed network, and receives and processes the image data to produce anomaly reports. Each process node has an interface card coupled to the first high speed network, that receives the image data from the first high speed network and formats the image data according to a high speed interface bus protocol. The interface card sets a register indicating whether a predetermined amount of image data has been stored in a memory, and the process node reads the register to determine whether the predetermined amount of image data has been stored in the memory, and initiates image processing when the register indicates that the predetermined amount of image data has been stored in the memory.


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