The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2014

Filed:

Jun. 21, 2010
Applicants:

Ik-soo Kim, Yongin-si, KR;

Sung-lae Cho, Gwacheon-si, KR;

Do-hyung Kim, Seongnam-si, KR;

Hyeong-geun an, Hwaseong-si, KR;

Dong-hyun Im, Hwaseong-si, KR;

Eun-hee Cho, Seoul, KR;

Inventors:

Ik-Soo Kim, Yongin-si, KR;

Sung-Lae Cho, Gwacheon-si, KR;

Do-Hyung Kim, Seongnam-si, KR;

Hyeong-Geun An, Hwaseong-si, KR;

Dong-Hyun Im, Hwaseong-si, KR;

Eun-Hee Cho, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC.


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