The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2014

Filed:

Dec. 15, 2006
Applicants:

Tim Thurgate, Sunnyvale, CA (US);

Shenqing Fang, Fremont, CA (US);

Kuo-tung Chang, Saratoga, CA (US);

Youseok Suh, Cupertino, CA (US);

Meng Ding, Sunnyvale, CA (US);

Hidehiko Shiraiwa, San Jose, CA (US);

Amol Joshi, Sunnyvale, CA (US);

Harpreet Sachar, Milpitas, CA (US);

David Matsumoto, San Jose, CA (US);

Lovejeet Singh, Sunnyvale, CA (US);

Chih-yuh Yang, San Jose, CA (US);

Inventors:

Tim Thurgate, Sunnyvale, CA (US);

Shenqing Fang, Fremont, CA (US);

Kuo-Tung Chang, Saratoga, CA (US);

YouSeok Suh, Cupertino, CA (US);

Meng Ding, Sunnyvale, CA (US);

Hidehiko Shiraiwa, San Jose, CA (US);

Amol Joshi, Sunnyvale, CA (US);

Harpreet Sachar, Milpitas, CA (US);

David Matsumoto, San Jose, CA (US);

Lovejeet Singh, Sunnyvale, CA (US);

Chih-Yuh Yang, San Jose, CA (US);

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.


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