The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2014

Filed:

Jun. 28, 2011
Applicants:

Zvi Or-bach, San Jose, CA (US);

Deepak Sekar, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Ze'ev Wurman, Palo Alto, CA (US);

Inventors:

Zvi Or-Bach, San Jose, CA (US);

Deepak Sekar, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Ze'ev Wurman, Palo Alto, CA (US);

Assignee:

Monolithic 3D Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.


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