The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2014
Filed:
Mar. 19, 2010
Zhe LI, Tianjin, CN;
Qingchun He, Tianjin, CN;
Guanhua Wang, Tianjian, CN;
Zhijie Wang, Tianjin, CN;
Nan Xu, Tianjin, CN;
Zhe Li, Tianjin, CN;
Qingchun He, Tianjin, CN;
Guanhua Wang, Tianjian, CN;
Zhijie Wang, Tianjin, CN;
Nan Xu, Tianjin, CN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.