The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2014
Filed:
Jul. 30, 2008
Emile Y. Sahouria, Sunnyvale, CA (US);
Alexander V. Tritchkov, Hillsboro, OR (US);
Emile Y. Sahouria, Sunnyvale, CA (US);
Alexander V. Tritchkov, Hillsboro, OR (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
Separation directives for integrated circuit layout design data are formed based upon one or more printing feasibility analyses performed on the layout design data. At least one printing feasibility analysis is performed on layout design data to identify portions of the design that may not be correctly formed or 'printed' during a photolithographic process. The geometric element edges involved in a potential printing defect are then identified as edges to be formed using separate masks. Further, separation directives may be created to specifically designate the identified edges as edges to be formed using separate masks in a photolithographic manufacturing process.