The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2014
Filed:
Jun. 16, 2010
Shin-jang Shen, Jhubei, TW;
Bo-chang Wu, Zhubei, TW;
Chuan Ying Yu, Zhubei, TW;
Ken-hui Chen, Hsinchu, TW;
Kuen-long Chang, Taipei, TW;
Chun-hsiung Hung, Hsinchu, TW;
Shin-Jang Shen, Jhubei, TW;
Bo-Chang Wu, Zhubei, TW;
Chuan Ying Yu, Zhubei, TW;
Ken-Hui Chen, Hsinchu, TW;
Kuen-Long Chang, Taipei, TW;
Chun-Hsiung Hung, Hsinchu, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.