Vertical parasitic pnp device in a bicmos process and manufacturing method of the same

Abstract

The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.