The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2014

Filed:

Mar. 15, 2012
Applicants:

Dureseti Chidambarrao, Hopewell Junction, NY (US);

Sunfei Fang, Hopewell Junction, NY (US);

Yue Liang, Hopewell Junction, NY (US);

Xiaojun Yu, Hopewell Junction, NY (US);

Jun Yuan, Hopewell Junction, NY (US);

Inventors:

Dureseti Chidambarrao, Hopewell Junction, NY (US);

Sunfei Fang, Hopewell Junction, NY (US);

Yue Liang, Hopewell Junction, NY (US);

Xiaojun Yu, Hopewell Junction, NY (US);

Jun Yuan, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.


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