The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2013
Filed:
Mar. 09, 2012
Applicants:
Cheok-kei Lei, Andar AC, MO;
Yi-tang Lin, Hsinchu, TW;
Hsiao-hui Chen, Hsinchu, TW;
Yu-ning Chang, Hsinchu, TW;
Shu-yu Chen, Hsinchu, TW;
Chien-wen Chen, Hsinchu, TW;
Chih-sheng Chang, Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Inventors:
Cheok-Kei Lei, Andar AC, MO;
Yi-Tang Lin, Hsinchu, TW;
Hsiao-Hui Chen, Hsinchu, TW;
Yu-Ning Chang, Hsinchu, TW;
Shu-Yu Chen, Hsinchu, TW;
Chien-Wen Chen, Hsinchu, TW;
Chih-Sheng Chang, Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.