The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2013
Filed:
Sep. 13, 2012
John B. Campi, Westford, VT (US);
Shunhua Thomas Chang, South Burlington, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Junjun LI, Williston, VT (US);
Rahul Mishra, Essex Junction, VT (US);
Mujahid Muhammad, Essex Junction, VT (US);
John B. Campi, Westford, VT (US);
Shunhua Thomas Chang, South Burlington, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Junjun Li, Williston, VT (US);
Rahul Mishra, Essex Junction, VT (US);
Mujahid Muhammad, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.