The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2013
Filed:
May. 25, 2011
Chien-liang Lin, Taoyuan County, TW;
Gin-chen Huang, Taipei County, TW;
Ying-wei Yen, Miaoli County, TW;
Yu-ren Wang, Tainan, TW;
Chien-Liang Lin, Taoyuan County, TW;
Gin-Chen Huang, Taipei County, TW;
Ying-Wei Yen, Miaoli County, TW;
Yu-Ren Wang, Tainan, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.