The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2013

Filed:

Jan. 05, 2009
Applicants:

Mani Ayyar, Cupertino, CA (US);

Srinivas Chennupaty, Portland, OR (US);

Akhilesh Kumar, Sunnyvale, CA (US);

Doddabaliapur Narasimha-murthy Jayasimha, Sunnyvale, CA (US);

Murugasamy Nachimuthu, Hillsboro, OR (US);

Phanindra K. Mannava, Folsom, CA (US);

Ioannis T. Schoinas, Portland, OR (US);

Inventors:

Mani Ayyar, Cupertino, CA (US);

Srinivas Chennupaty, Portland, OR (US);

Akhilesh Kumar, Sunnyvale, CA (US);

Doddabaliapur Narasimha-Murthy Jayasimha, Sunnyvale, CA (US);

Murugasamy Nachimuthu, Hillsboro, OR (US);

Phanindra K. Mannava, Folsom, CA (US);

Ioannis T. Schoinas, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 13/00 (2006.01); G06F 15/16 (2006.01); G06F 15/177 (2006.01); H04L 12/42 (2006.01);
U.S. Cl.
CPC ...
Abstract

Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.


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