The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2013
Filed:
May. 04, 2012
Kiyotaro Itagaki, Yokohama, JP;
Yoshihisa Iwata, Yokohama, JP;
Hiroyasu Tanaka, Minato-ku, JP;
Masaru Kidoh, Komae, JP;
Masaru Kito, Yokohama, JP;
Ryota Katsumata, Yokohama, JP;
Hideaki Aochi, Kawasaki, JP;
Akihiro Nitayama, Yokohama, JP;
Takashi Maeda, Yokohama, JP;
Tomoo Hishida, Yokohama, JP;
Kiyotaro Itagaki, Yokohama, JP;
Yoshihisa Iwata, Yokohama, JP;
Hiroyasu Tanaka, Minato-ku, JP;
Masaru Kidoh, Komae, JP;
Masaru Kito, Yokohama, JP;
Ryota Katsumata, Yokohama, JP;
Hideaki Aochi, Kawasaki, JP;
Akihiro Nitayama, Yokohama, JP;
Takashi Maeda, Yokohama, JP;
Tomoo Hishida, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.