The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2013
Filed:
May. 14, 2012
Brian M. Henderson, San Diego, CA (US);
Ronnie A. Lindley, San Diego, CA (US);
Dong Wook Kim, San Diego, CA (US);
Reza Jalilizeinali, San Diego, CA (US);
Shiqun Gu, San Diego, CA (US);
Matthew M. Nowak, San Diego, CA (US);
Brian M. Henderson, San Diego, CA (US);
Ronnie A. Lindley, San Diego, CA (US);
Dong Wook Kim, San Diego, CA (US);
Reza Jalilizeinali, San Diego, CA (US);
Shiqun Gu, San Diego, CA (US);
Matthew M. Nowak, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.