The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Jun. 29, 2012
James D. Burrell, San Diego, CA (US);
Zhongping Bao, San Diego, CA (US);
Liang Cheng, San Diego, CA (US);
Damion B. Gastelum, San Diego, CA (US);
Gary D. Good, San Diego, CA (US);
Mohammed A. Tantoush, San Diego, CA (US);
Jon J. Anderson, Boulder, CO (US);
James D. Burrell, San Diego, CA (US);
Zhongping Bao, San Diego, CA (US);
Liang Cheng, San Diego, CA (US);
Damion B. Gastelum, San Diego, CA (US);
Gary D. Good, San Diego, CA (US);
Mohammed A. Tantoush, San Diego, CA (US);
Jon J. Anderson, Boulder, CO (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Various embodiments of methods and systems for heuristic determination and thermal analysis of component placement on a printed circuit board ('PCB') for use in a portable computing device ('PCD') are disclosed. It is an advantage of embodiments that thermal energy generating components, such as processors, may be heuristically selected and arranged on a selected PCB according to varying layouts and combinations and then evaluated for thermal dissipation efficiency under an assortment of use case scenarios. In this way, users of the system and method may quickly narrow down commercially feasible component layouts, identify the most efficient layouts and then heuristically modify the layouts to develop an optimal arrangement.