The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Jan. 16, 2012
Marc Tarabbia, Pleasant Valley, NY (US);
James B. Gullette, Dresden, DE;
Mahbub Rashed, Santa Clara, CA (US);
David S. Doman, Austin, TX (US);
Irene Y. Lin, Los Altos Hills, CA (US);
Ingolf Lorenz, Ottendorf-Okrilla, DE;
Larry Ho, Cupertino, CA (US);
Chinh Nguyen, Austin, TX (US);
Jeff Kim, San Jose, CA (US);
Jongwook Kye, Pleasanton, CA (US);
Yuansheng MA, Santa Clara, CA (US);
Yunfei Deng, Sunnyvale, CA (US);
Rod Augur, Hopewell Junction, NY (US);
Seung-hyun Rhee, Fishkill, NY (US);
Jason E. Stephens, Beacon, NY (US);
Scott Johnson, Wappingers Falls, NY (US);
Subramani Kengeri, San Jose, CA (US);
Suresh Venkatesan, Danbury, CT (US);
Marc Tarabbia, Pleasant Valley, NY (US);
James B. Gullette, Dresden, DE;
Mahbub Rashed, Santa Clara, CA (US);
David S. Doman, Austin, TX (US);
Irene Y. Lin, Los Altos Hills, CA (US);
Ingolf Lorenz, Ottendorf-Okrilla, DE;
Larry Ho, Cupertino, CA (US);
Chinh Nguyen, Austin, TX (US);
Jeff Kim, San Jose, CA (US);
Jongwook Kye, Pleasanton, CA (US);
Yuansheng Ma, Santa Clara, CA (US);
Yunfei Deng, Sunnyvale, CA (US);
Rod Augur, Hopewell Junction, NY (US);
Seung-Hyun Rhee, Fishkill, NY (US);
Jason E. Stephens, Beacon, NY (US);
Scott Johnson, Wappingers Falls, NY (US);
Subramani Kengeri, San Jose, CA (US);
Suresh Venkatesan, Danbury, CT (US);
GLOBALFOUNDRIES, Inc., Grand Cayman, KY;
Abstract
A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.