The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Oct. 18, 2011
Kevin C. Olson, Wexford, PA (US);
Alan G. Wang, Shanghai, CN;
Kevin C. Olson, Wexford, PA (US);
Alan G. Wang, Shanghai, CN;
PPG Industries Chio, Inc., Cleveland, OH (US);
Abstract
A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.