The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2013
Filed:
Mar. 16, 2010
Joel P. DE Souza, Putnam Valley, NY (US);
Masafumi Hamaguchi, White Plains, NY (US);
Ahmet S. Ozcan, Pleasantville, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Donald R. Wall, Poughkeepsie, NY (US);
Joel P. de Souza, Putnam Valley, NY (US);
Masafumi Hamaguchi, White Plains, NY (US);
Ahmet S. Ozcan, Pleasantville, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Donald R. Wall, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Toshiba America Electronic Components, Inc., Irvine, CA (US);
Abstract
An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.