The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2013

Filed:

Jul. 07, 2011
Applicants:

Shunpei Yamazaki, Setagaya, JP;

Mitsuhiro Ichijo, Zama, JP;

Makoto Furuno, Atsugi, JP;

Takashi Ohtsuki, Isehara, JP;

Kenichi Okazaki, Tochigi, JP;

Tetsuhiro Tanaka, Tochigi, JP;

Seiji Yasumoto, Tochigi, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Mitsuhiro Ichijo, Zama, JP;

Makoto Furuno, Atsugi, JP;

Takashi Ohtsuki, Isehara, JP;

Kenichi Okazaki, Tochigi, JP;

Tetsuhiro Tanaka, Tochigi, JP;

Seiji Yasumoto, Tochigi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiHand NO as source gases is in contact with the single-crystal semiconductor layer.


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