The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2013
Filed:
Sep. 22, 2011
Byung-lyul Park, Seoul, KR;
Gil-heyun Choi, Seoul, KR;
Suk-chul Bang, Yongin-si, KR;
Kwang-jin Moon, Suwon-si, KR;
Dong-chan Lim, Suwon-si, KR;
Deok-young Jung, Seoul, KR;
Byung-Lyul Park, Seoul, KR;
Gil-Heyun Choi, Seoul, KR;
Suk-Chul Bang, Yongin-si, KR;
Kwang-Jin Moon, Suwon-si, KR;
Dong-Chan Lim, Suwon-si, KR;
Deok-Young Jung, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.