The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2013

Filed:

Mar. 01, 2010
Applicants:

Munehiro Tada, Minato-ku, JP;

Yoshihiro Hayashi, Minato-ku, JP;

Yoshimichi Harada, Minato-ku, JP;

Fuminori Ito, Minato-ku, JP;

Hiroto Ohtake, Minato-ku, JP;

Tatsuya Usami, Kawasaki, JP;

Inventors:

Munehiro Tada, Minato-ku, JP;

Yoshihiro Hayashi, Minato-ku, JP;

Yoshimichi Harada, Minato-ku, JP;

Fuminori Ito, Minato-ku, JP;

Hiroto Ohtake, Minato-ku, JP;

Tatsuya Usami, Kawasaki, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layeris formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.


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