The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2013
Filed:
Jul. 22, 2011
Tsuo-wen LU, Kaohsiung, TW;
Tzung-ying Lee, Pingtung County, TW;
Jei-ming Chen, Tainan, TW;
Chun-wei Hsu, Taipei, TW;
Yu-min Lin, Tainan, TW;
Chia-lung Chang, Tainan, TW;
Chin-cheng Chien, Tainan, TW;
Shu-yen Chan, Changhua County, TW;
Tsuo-Wen Lu, Kaohsiung, TW;
Tzung-Ying Lee, Pingtung County, TW;
Jei-Ming Chen, Tainan, TW;
Chun-Wei Hsu, Taipei, TW;
Yu-Min Lin, Tainan, TW;
Chia-Lung Chang, Tainan, TW;
Chin-Cheng Chien, Tainan, TW;
Shu-Yen Chan, Changhua County, TW;
Other;
Abstract
A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor.